Muhammad Farhan Azmine

I am a fourth year PhD student with Computer Engineering major at Virginia Tech. I have more than 5 years of experience in developing complex RTL designs, IP subsystem integration and Verification. My research includes developing energy efficient hardware friendly machine learning algorithms using Python/C++ and designing/optimizing digital chips using SystemVerilog/VHDL that can deploy them for Edge AI applications

Projects by Domain: FPGA/ASIC • Data Analysis and Data Structure • Machine Learning

RTL design Projects: RTL design & Verification for FPGA/ASIC
Check out my RTL chip design & Verification projects focussed on FPGA/ASIC
Data Analysis (EDA) & Data Structure (OOP) projects
A collection of my critical projects for mastering OOP, data structures, algorithms, comprehensive data analysis including cleaning, preprocessing, EDA analysis and API linking
Traditional Machine learning models for real world predictions
Explore my the real world application projects for traditional ML related to Human Seizure Epilepsepsy detection; Income dividend, Sport-Analysis and Weather data prediction