Projects by Domain: FPGA/ASIC • Machine Learning • Data Analysis and Python Data Structure
RTL design Projects: RTL design & Verification for FPGA/ASICCheck out my RTL chip design & Verification projects focussed on FPGA/ASIC
Data Analysis (EDA) & Data Structure (OOP) projectsA collection of my critical projects for mastering OOP, data structures, algorithms and comprehensive data analysis including cleaning, preprocessing, and EDA