Muhammad Farhan Azmine

I am a fourth year PhD student with Computer Engineering major at Virginia Tech. I have more than 5 years of experience in developing complex RTL designs, IP subsystem integration and Verification. My research includes developing energy efficient hardware friendly machine learning algorithms using Python/C++ and designing/optimizing digital chips using SystemVerilog/VHDL that can deploy them for Edge AI applications

Protocol Design & SystemC Verification

UART Protocol Design
Designing RTL based Drivers for UART Communication
PS-PL UART Integration (Vivado Setup)
Integrating RTL UART Driver on FPGA fabric (PL) with ZynQ Processor (PS) in Vivado
SystemC testbench (Vitis Setup + Hardware Testing)
Real-time Hardware FPGA validation through PS-PL data transfer and SystemC testbench